What You'll Do As a member of Cisco’s Central DFT team, you’ll be responsible for architecting, implementing and verifying the ASIC Design-for-Test (DFT) features that support silicon screening, in-system test, debug and diagnostics. You are a hands-on technical lead who will drive DFT insertion of Scan/ATPG, MemoryBist, Jtag protocols and new innovative DFT IP. You will work closely with the ASIC design teams to enable the integration and validation of Test logic in all phases of the design and back-end implementation flows. You will be accountable for DFT feature sign-off for silicon tape-out and post-silicon validation. You will work with Hardware Platform, Diagnostic and ATE Test teams to validate all DFT silicon features and test patterns. Support silicon life-cycle qualit
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American Academy of Environmental Engineers and Scientists®
147 Old Solomons Island Road, Suite 303
Annapolis, MD 21401
410.266.3311 | FAX: 410.266.7653